Lecture 11

 

Hardware Software interface

Hardware            software

 

                

Hardware Software Intersection

• Design interface and aspects
  
• Execution time = # of instructions * execution time per instruction
  
• CCycles = # of instructions * CCycles Per Instruction
  
• Average Clock Cycle Per Instruction
  
  • A = 2
    
  • B = 4
    
  • C= 1
    
• Solution =    
  
• This solution depends on them happening just as often, this is naive
  
• Mix of instructions
  

10	A
6	B
4	C
20

 

• 
  
• Clock Cycles per Instruction multicycle machine
  
• Instruction types A,B,C
  
• Example
  
  • Suppose we have the following:
    
  • Where CPI is –clocks per instruction
    

Mc	ISA	Clock Cycles	CPI
A	A	250 picoseconds	2.0
B	A	500 picoseconds	1.2

• Which machine is faster by how much??
  

• CPU CC A = 2x
  
• CPU CC B = 1.2x
  
• Cpu time A = CPU clock cycles A * Clock cycle time for A
  
  • =x * 2.0 * 250ps = 500xps
    
• Cpu time B = x * 1.2 * 500ps = 600ps
  
• b/a = 600/500 = 1.2
  
• a = 1.2x faster
  

 

Processor Datapath and Control

• in a single cycle machine all instructions are carried out in a single cycle
  
• Fetch Execute Cycle
  

_LOOP

||    Fetch Instruction

||    Execute Instruction

||_    End Loop

 

FETCH / EXECUTE CYCLE

 

• Functioning of a Computer at the Lowest Level Virtual Machine
  
  • No compiling
    
  • Like interpreter
    
  • Sequential
    
• PC keeps track of where we are in the program
  
  • PC = Program Counter
    

Major Issues

• Single clock cycle per instruction
  
• Data path resource used at most once per instruction
  
• Need to replicate some data path resources if need more than once: memory, ALU/adders
  
• Timing, testing of single cycle
  
• Single cycle datapath
  

Single Cycle

• All instructions in one cycle
  
• Cycle needs to be equal to the time for longest instruction
  

How to Design a Processor

• Analyze instruction set =>datapath requirements
  
  • The meaning of each instruction is given by the register transfers
    
  • Datapath must include storage element for ISA registers
    
    • Possibly more
      
  • Datapath must support each register transfer
    
• Select set of datapath components and establish clocking methodology
  
• Assemble datapath meeting the requirements
  
• Analyze implementation of each instruction to determine setting of control points that effects the register transfer
  
• Assemble the control logic